ITSW 2010 - Call for Papers

CALL FOR PAPERS

Scope -- Submissions -- Key Dates -- Additional Information -- Committees

Scope

Since the inception of ITSW in 1994 chip geometries have shrunk from 500 to 32 nanometers with smaller geometries on the near horizon. Digital circuit speeds have moved from the 100-200 MHz range to 2-3 GHz and higher. This amazing shrinkage and speedup has been spurred by innovative algorithms, tools, and methodologies in all aspects of digital chip design and manufacturing. The widespread use of Test Synthesis coupled with powerful pre-silicon verification approaches is one factor that has enabled test to keep up with the increasing chip complexity.

This year ITSW returns to its original location at the University of California, Santa Barbara. This year’s workshop will look at all aspects of test synthesis such as system bringup, system debug tools and architectures, re-use of pre-silicon DFT structures for post-silicon testing, hand-off of test IP, defect modeling, system test coverage metrics, SiP testing, system-level diagnostic methods, emerging standards for embedded testing, No Trouble Found methods, dealing with variations and imperfections inherent in the manufacturing process etc. As always ITSW will consider papers in any area of Test Synthesis including, but not limited to:

Register Transfer Level DFT
High-Level/Behavioral Test Synthesis
System-on-a-Chip (SOC) DFT
Memory and Logic BIST
Test Synthesis for Debug and Diagnosis
DFT for Mixed-Signal Circuits
Test Resource Partitioning
Functional Verification
DFT for Emerging Technologies

Power and Noise-Aware Test
DFT for At-Speed Test
High-speed I/O test
Reducing the Cost of Test
Design for Manufacturing and Yield
Board and System Test
SER / Reliability
Test Synthesis for Reconfigurable Logic

Submissions

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To present recent research results at the workshop, please submit an extended abstract, one to three pages long, in PDF format, to the Program Chair by July 31, 2010. Acceptance notifications will be sent out on August 20, 2010. Please include the names, affiliations, and full contact information of all authors. Also, indicate which author will be the speaker if the abstract is accepted for presentation. To support open discussion, no formal proceedings of the workshop will be published. As in previous years, ITSW will present a BEST Student Paper Award to encourage student participation in the workshop.

Key Dates

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Submission deadline: July 31, 2010
Notification of acceptance: August 20, 2010

Additional Information

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For general information, contact:
Abhijit Jas, General Chair
Design and Technology Solutions
Intel Corporation, Austin, TX 78746
Phone: 512.732.3978
FAX: 512.732.3912
Email: generalchair@tttc-itsw.org

Submit extended abstracts via email to:
Kedarnath Balakrishnan, Program Chair
7171 SouthWest Pkwy M/S B400.4A
Advanced Micro Devices, Austin, TX 78735
Phone: 512.602.0730
FAX: 512.602.2581
Email: programchair@tttc-itsw.org

Committees

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General Chair
A. Jas – Intel

Past Chair
J. Dworak – SMU Dallas

Program Chair
K. Balakrishnan – AMD

Finance Chair
S. Chakravarty - LSI

Panels Chair
S. Khatri – Texas A&M U.

Embedded Tutorials Chair
S. Patil – Intel

Publicity Chair
B. Foutz – Cadence

Local Arrangements Chair
Li-C. Wang – UC Santa Barbara

European Liaison
M. Zwolinski – U. Southampton

Asian Liaison
C. W. Wu – Nat. Tsing Hua U.

Program Committee
M. Abadir – Freescale
R. Aitken – ARM
C. Barnhart – SiliconAid
K. Chakrabarty – Duke U.
V. Chickermane – Cadence
K.-T.Cheng – UC Santa Barbara
A. Crouch – Asset-Intertech
R. Datta – Nvidia
S. Davidson – Oracle
C. Dixit – LSI
A. Guettaf – Broadcom
M. Hsiao – Virginia Tech.
K. Iwasaki – Tokyo Metro. U.
R. Kapur – Synopsys
M. Laisne – QualComm
K.-J. Lee – Nat. Cheng-Kung U.
A. Majumdar – AMD
S. Mitra - Stanford
K. Mohanram - Rice U.
M. Nourani –U. Texas, Dallas
A. Orailoglu – UC San Diego
B. Pouya – Freescale
J. Qian – Cisco
J. Rajski – Mentor Graphics
S. M. Reddy – U. Iowa
M. Tahoori – Northeastern U.
S. Tragoudas – S. Illinois U.
H. Walker – Texas A&M U.

For more information, visit us on the web at: http://www.tttc-itsw.org

The 17th International Test Synthesis Workshop (ITSW10) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC) and the IEEE Computer Society Design Automation Technical Committee.